SystemVerilog
使用SystemC建模SystemVerilog状态机的实例
通过一个状态机的例子可以比较好的理解SystemC怎么建模RTL。 我们以一个典型的SystemVerilog编写的状态机为例。 fsm.sv: module fsm( input clk, input rst_n, input [1:0] in, output logic [1:0] out ); ......
systemverilog中fork..join, join_any, join_none的用法和解析
对fork.. join, join_any以及join_none的用法进行总结,以及整理下可能遇到的坑。 简单的说就是: fork..join: 必须等到ment1,ment2,ment3全部执行完之后,ment4才可以执行。 fork..join_any: 等到ment1,ment2,ment3 ......
VSCODE ——SystemVerilog模板
{ // Place your snippets for verilog here. Each snippet is defined under a snippet name and has a prefix, body and // description. The prefix is what ......
SystemVerilog Dynamic Array Randomization
https://verificationguide.com/systemverilog/systemverilog-dynamic-array-randomization/ Dynamic Array Randomize For a dynamic array, it is possible to ......
SystemVerilog编码技巧
# 工程组织 可以将一些公用的变量定义成package,放到同一个sv文件中,然后在需要用到公用变量的文件中通过import来引用变量,创建filelist时,需要通过+incdir+(包含package的sv文件的路径)来指示,并将这些package的sv列在其他sv前面 ``` package ......
SystemVerilog总结
## SystemVerilog总结 过了两个月的时间,把这本《SystemVerilog for Design (Edition 2)》基本上读完了。对SystemVerilog也建立了一些认识。 本书一共十二章,除去第一章是比较笼统的介绍,最后两章主要是设计实例以外,第二章到第十章都是很干货的语 ......
SystemVerilog for Design Edition 2 Chapter 10
## SystemVerilog for Design Edition 2 Chapter 10 SystemVerilog extends the Verilog language with a powerful interface construct. Interfaces offer a ne ......
SystemVerilog读取文件的一个有趣现象(feof多读一次的问题)
在学习SystemVerilog读取文件时,练习读取自身的代码,代码如下: 1 module Test; 2 int file; 3 4 initial 5 begin 6 string s; 7 file = $fopen("TestFile.sv", "r"); 8 while(!$feof(f ......
SystemVerilog for Design Edition 2 Chapter 9
## SystemVerilog for Design Edition 2 Chapter 9 This chapter presents the many enhancements to Verilog that SystemVerilog adds for representing and wo ......
SystemVerilog for Design Edition 2 Chapter 8
## SystemVerilog for Design Edition 2 Chapter 8 SystemVerilog enables modeling at a higher level of abstraction through the use of 2-state types, enum ......
SystemVerilog接口练习
结合《SystemVerilog验证测试平台编写指南》和《FPGA应用开发和仿真》,在gVim里敲代码,学习一下接口的用法。 1 interface membus 2 #( 3 parameter LEN = 256, DW = 8 4 ) 5 ( 6 input wire clk, 7 input ......
SystemVerilog练习(结构体加队列)
《SystemVerilog验证测试平台编写指南》,刚刚学完队列和结构体,就想练习一下。 1 module TestStruct; 2 typedef struct packed 3 { 4 bit [7:0] addr; 5 bit [7:0] pr; 6 bit [15:0] data; 7 } ......
合并数组与非合并数组 -- SystemVerilog
合并型数组(packed): 合并型数组可以实现连续的存储,赋值时不需要用 ’{ }。 数组中,数据排列为{ b_pack[2], b_pack[1], b_pack[0] },其中每个b_pack为8个bit; bit是二值逻辑,每位bit只占据1位。故24位(8 bit * 3)只占据一个wor ......
SystemVerilog for Design Edition 2 Chapter 7
## SystemVerilog for Design Edition 2 Chapter 7 SystemVerilog adds several new operators and procedural statements to the Verilog language that allow ......
记录第一次练习使用SystemVerilog的logic声明
在学习状态机的编码方式,按照我个人的理解,将电路划分为输入方程,状态方程,输出方程。时序电路的设计,大多都是遵循这三个方程来进行。 在输出方程里,有两种描述方法: // 输出方程:方案一 assign sm_out = ( current_state == state_C ); // 输出方程:方案 ......
SystemVerilog for Design Edition 2 Chapter 6
## SystemVerilog for Design Edition 2 Chapter 6 The Verilog language provides a general purpose procedural block, called always, that is used to model ......
SystemVerilog for Design Edition 2 Chapter 5
## SystemVerilog for Design Edition 2 Chapter 5 SystemVerilog adds several enhancements to Verilog for representing large amounts of data. The Verilog ......
AI芯片与SystemVerilog参数化
AI芯片与SystemVerilog参数化 大模型引发技术变革, AI芯片公司面临新挑战 ChatGPT 在全球范围内掀起了一场技术革命与商业浪潮,AI 市场也迎来了前所未有的机遇与增量。 当前,AI 基础设施的算力、算法呈现新 “摩尔定律”:相同算力下能训练生产更优质的模型,同时最先进的 AI 模 ......
SystemVerilog for Design Edition 2 Chapter 3
SystemVerilog for Design Edition 2 Chapter 3 SystemVerilog extends Verilog’s built-in variable types, and enhances how literal values can be specified ......
SystemVerilog for Design Edition 2 Chapter 2
SystemVerilog for Design Edition 2 Chapter 2 SystemVerilog Declaration Spaces Verilog only has limited places in which designers can declare variables ......
SystemVerilog for Design Edition 2 Chapter 1
SystemVerilog for Design Edition 2 Chapter 1 Introduction to SystemVerilog: This chapter provides an overview of SystemVerilog. The topics presented i ......
SystemVerilog for Design Edition 2 Catalog
SystemVerilog for Design Edition 2 Catalog Part 10: The 2022 Wilson Research Group Functional Verification Study - Verification Horizons (siemens.com) ......
SystemVerilog 断言 (SVA) 与 Xilinx Vivado 2020
SystemVerilog 断言 (SVA) 与 Xilinx Vivado 2020.1 来自前 Amazon 招聘经理的系统设计面试内幕贴士——外加 6 次模拟面试练习! 课程英文名:SystemVerilog Assertions (SVA) with Xilinx Vivado 2020.1 ......