结果自动对比

`timescale 1ns/1ns
module tb;
reg CLK;
reg RSTN;
reg [3:0] R_in;
reg [3:0] Q_in;
reg START_in;
reg  [7:0]expP_out;
wire [7:0] P_out;
wire DONE;

parameter CYCLE=10;



Multiplier U0(
     .CLK(CLK),
  .RSTN(RSTN),
    .R_in(R_in),
    .Q_in(Q_in),
    .START_in(START_in),
   .P_out(P_out),  
  .DONE(DONE)
 );


initial begin
CLK=0;
  forever begin
 #(CYCLE/2)
 CLK=1;
 #(CYCLE/2)
 CLK=0;
  end
end


initial begin
	 RSTN = 0;
 	#(5*CYCLE);
	 RSTN = 1;
end




initial begin
		START_in=0;
		#(CYCLE*8)
	   forever begin
	 	 START_in=1;
	 	#(CYCLE*30)
	 	START_in=0;
	 	#(CYCLE*5)
	 	START_in=1;
	 	    end
	end


initial begin
R_in=0;Q_in=0;
	#(CYCLE*7)
	expP_out=0;
	#(CYCLE*21)
@(posedge START_in);
R_in=5;Q_in=6;
	#(33*CYCLE)

R_in=7;Q_in=8;
	#(33*CYCLE)
	
R_in=6;Q_in=9;
	#(33*CYCLE)

R_in=0;Q_in=15;
	#(33*CYCLE)

R_in=15;Q_in=0;
	#(33*CYCLE)

R_in=0;Q_in=0;
	#(33*CYCLE)

R_in=15;Q_in=15;
	#(33*CYCLE)

#(CYCLE*50)
	$finish;
end

task t_b;
input  [3:0]  expR_in;
input  [3:0]  expQ_in;
output [7:0]  expP_out;
  begin
        expP_out=expQ_in*expR_in;
  end
endtask

initial  begin
   forever  begin
     @DONE;
     
     t_b(Q_in,R_in,expP_out);
     #(4*CYCLE);
     if({P_out}!=={expP_out})
     $display($time,"NG:R_in=%d,Q_in=%d,P_out=%d,expP_out=%d",R_in,Q_in,P_out,expP_out);
       else
       $display($time,"OK:R_in=%d,Q_in=%d,P_out=%d,expP_out=%d",R_in,Q_in,P_out,expP_out);
   end
end
endmodule