SystemVerilog练习(结构体加队列)

 1 module TestStruct;
 2     typedef struct packed
 3     {
 4         bit [7:0] addr;
 5         bit [7:0] pr;
 6         bit [15:0] data;
 7     } Packet;
 8 
 9     Packet scb[$];
10     
11     function void check_addr(bit [7:0] addr);
12         int intq[$];
13         
14         intq = scb.find_index() with (item.addr == addr);
15         case(intq.size())
16             0:$display("Addr %0b not found in scoreboard", addr);
17             1:begin
18                 $display("Find result: pr=%0b, data=%0b",scb[intq[0]].pr, scb[intq[0]].data);
19                 scb.delete(intq[0]);
20               end
21             default:$display("Error:Multiple hits for addr %0b",addr);
22         endcase
23     endfunction:check_addr
24 
25     initial
26     begin
27         static Packet var1 = {8'b1, 8'b11, 16'b111};
28         static Packet var2 = {8'b11, 8'b111, 16'b1111};
29         static Packet var3 = {8'b111, 8'b1111, 16'b11111};
30         static Packet var4 = {8'b111, 8'b1111, 16'b11111};
31 
32         scb.insert(0, var1);
33         scb.push_back(var2);
34         scb.push_front(var3);
35         scb.insert(scb.size(), var4);
36 
37         foreach(scb[i])
38             $display("index=%0d, addr=%0b, pr=%0b, data=%0b",i, scb[i].addr, scb[i].pr, scb[i].data);
39         check_addr(8'b1);
40         check_addr(8'b1);
41         check_addr(8'b111);
42         
43         foreach(scb[i])
44             $display("index=%0d, addr=%0b, pr=%0b, data=%0b",i, scb[i].addr, scb[i].pr, scb[i].data);
45     end
46 endmodule